{% if target['core'] == 'cpuapp' %}
/dts-v1/;
#include <nordic/{{ soc }}_{{ target['core'] }}.dtsi>
#include "{{ board }}-pinctrl.dtsi"

/ {
	model = "{{ board_desc }}";
	compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuapp";

	chosen {
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &cpuapp_sram;
		zephyr,flash = &cpuapp_rram;
	};
};

&cpuapp_sram {
	status = "okay";
};

&grtc {
	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
	child-owned-channels = <3 4 7 8 9 10 11>;
	status = "okay";
};

&cpuapp_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x0 DT_SIZE_K(64)>;
		};
		slot0_partition: partition@10000 {
			label = "image-0";
			reg = <0x10000 DT_SIZE_K(324)>;
		};
		slot0_ns_partition: partition@61000 {
			label = "image-0-nonsecure";
			reg = <0x61000 DT_SIZE_K(324)>;
		};
		slot1_partition: partition@b2000 {
			label = "image-1";
			reg = <0xb2000 DT_SIZE_K(324)>;
		};
		slot1_ns_partition: partition@103000 {
			label = "image-1-nonsecure";
			reg = <0x103000 DT_SIZE_K(324)>;
		};
		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
		storage_partition: partition@15c000 {
			label = "storage";
			reg = <0x15c000 DT_SIZE_K(36)>;
		};
	};
};
{% else %}
{% if not target['xip'] %}
/dts-v1/;
#include <nordic/{{ soc }}_{{ target['core'] }}.dtsi>
#include "{{ board }}-pinctrl.dtsi"

/ {
	model = "{{ board_desc }}";
	compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuflpr";

	chosen {
		zephyr,code-partition = &cpuflpr_code_partition;
		zephyr,flash = &cpuflpr_rram;
		zephyr,sram = &cpuflpr_sram;
	};
};

&cpuflpr_sram {
	status = "okay";
	reg = <0x20028000 DT_SIZE_K(96)>;
	ranges = <0x0 0x20028000 DT_SIZE_K(96)>;
};

&cpuflpr_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		cpuflpr_code_partition: partition@0 {
			label = "image-0";
			reg = <0x0 DT_SIZE_K(96)>;
		};
	};
};

&grtc {
	owned-channels = <3 4>;
	status = "okay";
};
{% else %}
#include "{{ board }}_{{soc}}_cpuflpr.dts"

/ {
	compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuflpr-xip";
};

&cpuflpr_sram {
	reg = <0x2002f000 DT_SIZE_K(68)>;
	ranges = <0x0 0x2002f000 DT_SIZE_K(68)>;
};
{% endif %}
{% endif %}
